/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R9A08G045S_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R9A08G045S_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r9a08g045s CPG Core Clocks */
#define R9A08G045S_CLK_I		0
#define R9A08G045S_CLK_I2		1
#define R9A08G045S_CLK_I3		2
#define R9A08G045S_CLK_P0		3
#define R9A08G045S_CLK_P1		4
#define R9A08G045S_CLK_P2		5
#define R9A08G045S_CLK_P3		6
#define R9A08G045S_CLK_P4		7
#define R9A08G045S_CLK_P5		8
#define R9A08G045S_CLK_TSU		9
#define R9A08G045S_CLK_SD0		10
#define R9A08G045S_CLK_SD1		11
#define R9A08G045S_CLK_SD2		12
#define R9A08G045S_CLK_SPI0		13
#define R9A08G045S_CLK_SPI1		14
#define R9A08G045S_CLK_AT		15
#define R9A08G045S_CLK_ZT		16
#define R9A08G045S_CLK_M0		17
#define R9A08G045S_CLK_S0		18
#define R9A08G045S_CLK_HP		19
#define R9A08G045S_CLK_OC0		20
#define R9A08G045S_CLK_OC1		21
#define R9A08G045S_OSCCLK		22
#define R9A08G045S_OSCCLK2		23

/* r9a08g045s Module Clocks */

#define R9A08G045S_CLK_GIC600		0
#define R9A08G045S_CLK_IA55		1
#define R9A08G045S_CLK_SYC		2
#define R9A08G045S_CLK_DMAC		3
#define R9A08G045S_CLK_SYSC		4
#define R9A08G045S_CLK_MTU		5
#define R9A08G045S_CLK_ETH0		6
#define R9A08G045S_CLK_ETH1		7
#define R9A08G045S_CLK_I2C0		8
#define R9A08G045S_CLK_I2C1		9
#define R9A08G045S_CLK_I2C2		10
#define R9A08G045S_CLK_I2C3		11
#define R9A08G045S_CLK_SCIF0		12
#define R9A08G045S_CLK_SCIF1		13
#define R9A08G045S_CLK_SCIF2		14
#define R9A08G045S_CLK_SCIF3		15
#define R9A08G045S_CLK_SCIF4		16
#define R9A08G045S_CLK_SCIF5		17
#define R9A08G045S_CLK_SCI0		18
#define R9A08G045S_CLK_SCI1		19
#define R9A08G045S_CLK_GPIO		20
#define R9A08G045S_CLK_SDHI0		21
#define R9A08G045S_CLK_SDHI1		22
#define R9A08G045S_CLK_SDHI2		23
#define R9A08G045S_CLK_USB0		24
#define R9A08G045S_CLK_USB1		25
#define R9A08G045S_CLK_CANFD		26
#define R9A08G045S_CLK_MHU		27
#define R9A08G045S_CLK_OSTM0		28
#define R9A08G045S_CLK_OSTM1		29
#define R9A08G045S_CLK_OSTM2		30
#define R9A08G045S_CLK_OSTM3		31
#define R9A08G045S_CLK_OSTM4		32
#define R9A08G045S_CLK_OSTM5		33
#define R9A08G045S_CLK_OSTM6		34
#define R9A08G045S_CLK_OSTM7		35
#define R9A08G045S_CLK_WDT0		36
#define R9A08G045S_CLK_WDT1		37
#define R9A08G045S_CLK_WDT2		38
#define R9A08G045S_CLK_RSPI0		39
#define R9A08G045S_CLK_RSPI1		40
#define R9A08G045S_CLK_RSPI2		41
#define R9A08G045S_CLK_RSPI3		42
#define R9A08G045S_CLK_RSPI4		43
#define R9A08G045S_CLK_ADC		44
#define R9A08G045S_CLK_SPI		45
/* Note: TSU_PCLK macro is always placed at highest number */
#define R9A08G045S_CLK_TSU_PCLK		46

#endif /* __DT_BINDINGS_CLOCK_R9A08G045S_CPG_H__ */
